Logic Circuits Timing Analysis Using Timed Logic Variables
نویسندگان
چکیده
منابع مشابه
Variable Delay Timing Analysis of Logic Circuits
We propose a new simulation algorithm for combinational circuits which accurately models delay variations in the gates. The algorithm can also be used for the timing veriication of asynchronous circuits, eg hazard detection, race/oscillation of sequential circuits, etc. The basic idea is to assign a time variable to each signal transition (edge). The gate delays translate to algebraic relations...
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ژورنال
عنوان ژورنال: European Scientific Journal, ESJ
سال: 2016
ISSN: 1857-7431,1857-7881
DOI: 10.19044/esj.2016.v12n18p35